You are required to design a simple CMOS circuit consisting of a two-input NOR gate. You are required to show the layout (plan view) of the circuit, after calculating the aspect ratio (W?L) of the transistors. The Layout of the circuit includes the VDD and ground lines.
Designing a simple CMOS circuit consisting of two-input NOR gate.
The schematic shows that there are 2 P-MOS Transistors (Pull up Network) in Parallel and 2 N-MOS Transistors in Series (Pull down Network).
When A or B is high inputs, M1 or M2 will be ohmic and the output F will discharge to zero.
When both A and B are low inputs, Mp1 or Mp2 will be the output F will charge to Vdd.
Using Cadence Virtuoso to draw the layout and verify the design rules and the simulations results for 2-input NOR gate.
Following these steps to draw the layout:
Drawing Transistors To make p and n transistors. For p transistor using n-well and the background in the main layout window will act as your p-substrate. Thus the n transistors is placed directly in the p substrate. However the p transistor will be placed in n-well. Masks used for P transistor: N-well, diffusion, any poly. Masks used for N transistor: P-substrate, diffusion, any poly.
Making Connection The next step is to connect the drains of the two N transistors and the first P transistor together to make up the output. The source of the first P transistor is connected to the drain of the second P transistor which is source is connected to Vdd and the source of the two N transistors are connected to Gnd. The two gates of each (N and P) transistor are connected together to form one of the inputs. Metal 1: used for input A, and B. Metal 2: used for output, Vdd, and Gnd.
Drawn layers (Masks) used to create a transistor:
Well: NMOS are in P-well, PMOS are in N-well.
Diffusion: defines active vs. isolation regions on layout, and sets Source and Drain for transistor.
Poly: gate mask over diffusion mask defines W and L of each transistor.
Contact: defines the contacts between the masks.
Tap: defines contact to substrate or well.
List of Rules to be Considered:
One layer: width, spacing
layer to layer: spacing, enclosure, extension, overlap
Rules are going to be separated into the masks: N-well, Diffusion, Poly, Contact, and Metal
Explanation of Layout:
Layout PMOS and NMOS Transistors using calculated W/L)p, W/L)n using Diffusion, Poly and Well Masks.